Investigation of Wafer Surface Static Electricity in Lithography Process

Lithography is one of the most important processes in integrated circuit manufacturing, by which the prepared patterns from mask are transferred onto wafer via photochemical reaction.After lithography processes, the critical dimension (CD) of patterns are measured normally by secondary electron microscope (SEM).In the CD-SEM measurement process of ultra-thick metal layer of 14nm technology, the detected measurement target of wafer center is shifted from registered coordinates, while the other measurement area is normal.The inspection methods including overlay (OVL), wafer leveling, resist thickness, after etching inspection (AEI) and surface potential measurement are carried out to excluding other influence factor of shift.And combined with wafer surface potential measurement, the phenomenon of charge accumulation on wafer surface after lithography has been verified.The interaction between static electricity of wafer center and incidence electrons of SEM causes the measurement issue.Further, the origin and producing mechanism of charge on wafer are clarified by a series of experiments.Finally, this issue is improved by modifying development process of lithography.