Time scaling methodology for superconducting dual-active-layer integrated circuits

The concept of time scaling, recently introduced by researchers, establishes the time constant τ as a unified optimization objective across hierarchical levels, positing that the continuous compression of critical timing paths drives progress from devices to systems. Semiconductor Logic Folding, implemented via package-level or wafer-bonding three-dimensional integration, exemplifies this concept within the complementary metal-oxide-semiconductor (CMOS) domain. This paper proposes a dual-active-layer time-scaling perspective for superconducting single-flux-quantum (SFQ) circuits. In contrast to Semiconductor Logic Folding, which relies primarily on package-level reconstruction, superconducting circuits enable the direct fabrication of dual active device layers within a monolithic wafer process stack, thereby facilitating three-dimensional compression of logic paths. We analyze the role of the dual-active-layer architecture in enhancing effective device utilization, alleviating planar layout congestion, shortening SFQ pulse propagation paths, and advancing τ-aware design automation, thus providing a theoretical basis for performance improvements in superconducting integrated circuits in the post-Moore era.