Research on the co-design technology of layout-level drift region scaling and segmented field plate engineering for LDMOS

This study addresses the inherent trade-off between manufacturing cost and device performance in high-voltage N-type laterally diffused metal-oxide-semiconductor (NLDMOS) devices fabricated using a standard 0.15 μm BCD (bipolar-CMOS-DMOS) process. A layout-level co-optimization strategy is proposed, integrating drift region scaling with segmented field plate engineering. The approach aims to overcome the limitations of the conventional "space-for-breakdown-voltage" paradigm without introducing additional photomasks or process steps. By employing segmented polysilicon field plates, the surface electric field is effectively re-modulated, mitigating electric field crowding caused by the aggressive reduction of critical drift region dimensions, including the accumulation region (L_acc), source field plate (L_FP), and drift region extension (L_gap). Technology computer-aided design (TCAD) simulation results indicate that the optimized device achieves significant reductions in both cell pitch and current transmission path length while maintaining robust voltage-withstanding capabilities. The breakdown voltage (V_BR) is slightly improved to 54.32 V. Furthermore, the specific on-resistance (R_on,sp) is reduced by 31.7%, decreasing from 28.22 mΩ·mm² to 19.27 mΩ·mm². The Baliga figure of merit (BFOM) is enhanced by 47.5%, reaching 153.1 V²·mΩ⁻¹·mm⁻². This work achieves a dual breakthrough in device integration density and electrical performance, offering a cost-effective technical solution for the design of high-performance power management integrated circuits (PMICs).