Effects of buffer layer types and high-temperature control on the performance of new SOSiC PIN diodes

Silicon-on-SiC (Si-on-SiC, SOSiC) wafers are more suitable for radio frequency and power device fabrication than conventional SOI wafers owing to their higher thermal conductivity. In this study, SOSiC-1 wafers with a nanometer-scale amorphous Si buffer layer and SOSiC-2 wafers with an approximately 10 nm SiO₂ buffer layer were prepared. PIN diodes were fabricated on these SOSiC wafers and on conventional SOI materials for comparative analysis. The SOI PIN diode burned out when the power per unit width reached 0.0122 W·μm⁻¹, whereas the two SOSiC PIN diodes continued to operate and withstand higher voltages at power densities exceeding this value, indicating the potential advantages of SOSiC wafers for high-power device fabrication. Moreover, the leakage current of the SOSiC-2 PIN diodes was only one-third to one-fifth that of the SOSiC-1 PIN diodes, suggesting that introducing a buffer layer of appropriate thickness between Si and SiC can further improve device performance while maintaining effective heat dissipation. These results indicate that using a ~10 nm SiO₂ buffer layer at the Si/SiC interface in SOSiC materials can simultaneously enhance heat dissipation and maintain excellent electrical performance, showing great promise for high-power-density integrated applications.