Abstract: With the advent of the Internet of Things era, the traditional sensor chip and memory chip separation architecture can no longer meet the needs of practical scenarios.3D integration technology can shorten the physical distance between the sensor chip and the memory chip, realize the function expansion, and improve the energy efficiency of the system.Wafer-level integration has always been a research hotspot in academia and industry due to its high alignment accuracy and high interconnection density.This paper systematically introduces two mainstream processes in wafer-level integration technology, including through-silicon via and hybrid bonding processes.Combined with the latest progress of many research institutions at home and abroad, its development direction is prospected to realize the wafer-level integration process suitable for sensing-memory-computing integrated chips.