28 nm CMOS技术平台STI填充工艺中Seam Free工艺研究

Novel seam-free gap fill process for STI in 28 nm CMOS technology

  • 摘要: 对28 nm CMOS工艺平台中具有“高深宽比”的“非标准V型”STI结构进行探讨。采用传统的HARP和Post Steam高温退火组合工艺,研究了该结构的Seam Free填充方案。通过交叉实验,分别验证了HARP沉积新工艺和高温退火新工艺对HARP氧化硅薄膜收缩率的影响,以及对高深宽比沟槽Seam的作用。实验结果表明,通过HARP沉积新工艺与脉冲式高温退火并引入HCl辅助气体的协同作用,可有效解决28nm CMOS工艺平台中“高深宽比”的“非标准V型”STI结构的Seam问题。

     

    Abstract: This study explores a seamless filling solution for "non-standard V-shaped" shallow trench isolation (STI) structures with high aspect ratios within a 28 nm CMOS process platform. The investigation utilizes the conventional High Aspect Ratio Process (HARP) in combination with post-steam high-temperature annealing. Through systematic cross-experiments, the effects of the modified HARP deposition process and the high-temperature annealing process on the shrinkage rate of HARP silicon oxide films were analyzed. Additionally, their influence on seam formation in high-aspect-ratio trenches was evaluated. The results indicate that the integration of the optimized HARP deposition process with pulsed high-temperature annealing, incorporating HCl as an auxiliary gas, effectively addresses seam-related challenges in high-aspect-ratio, non-standard V-shaped STI structures within the 28 nm CMOS process platform.

     

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