Abstract: Power dissipation is regarded as one of the top concerns in VLSI digital system, and reducing working voltage is greatly helpful for reducing power consumption. Based on the analysis of the factors affecting threshold voltage（V_T）, technology and circuit methods were used to a djust V_T. Dual threshold voltages were applied in design of a low voltage Booth Multiplier, in which a small number of devices that are speed-critical operate at a relatively low V_T to deal with time delay,and other devices operate at higher V_T to avoid excessive leakage current. Simulation result shows that power dissipation can be decreased to 10% when working voltage change from 3.3V to 1.0V, and time delay is still kept in restrict range.