Abstract: Chip scale package （CSP） is a new microelectronic packaging technology rapidly deve- loped in recent years. The failure of the gold wires of CSP is analyzed by the Finite Element Analysis Software-ANSYS. The stress on gold wire is found to be subject to the CTE （Coefficient of Temperature Expansion） of mold compound, ball bond radius, wire radius and wire high. The maximum stress （SEQV_max=625.202 MPa）, due to thermal mismatch, is located on the root of wire. The results from both experiment and simulation show that the failure of package usually occurred on this location. It is found that the minimum stress of the wire （SEQV_max=113.723 MPa）, which is about 1/6 of the formal when the CTE of mold equals to 1.0×10^-5/℃, and that the stress of the wire decreases with the decrease of the wire radius and the increase of the ball bond radius.