Abstract: In very large-scale integrated (VLSI) circuit manufacturing, CMP is essential for achieving global surface flatness across multilayer metal interconnects, significantly influencing lithographic precision and electrical performance. This study focuses on the optimization of CMP modeling, particularly in the accurate prediction of hotspot patterns with unique geometries. Experimental comparisons with atomic force microscopy (AFM) measurements indicate that conventional 20 μm grid windows are inadequate for capturing localized Erosion defects. A refined strategy employing 3 μm grid windows with a 1.5 μm offset is introduced, markedly enhancing prediction accuracy. This method not only identifies process-sensitive regions within the layout but also facilitates the tracking of Erosion-induced variations in metal thickness across higher metal layers. The findings underscore the critical role of grid resolution and positioning in CMP modeling and offer a reliable approach to improving IC yield and manufacturing robustness.