CMOS/SOI 4kb静态随机存储器
CMOS/SOI 4kb SRAM
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摘要: 对一种CMOS/SOI 4kb静态随机存储器进行了研究,其电路采用1k×4的并行结构体系。为了提高电路的速度和降低功耗,采用地址转换监控Address-Translate-Detector(ATD)、两级字线Double-Word-Line(DWL)和新型的两级灵敏放大等技术,其地址取数时间为30ns,最小动态工作电流为30mA(工作电压5V,工作频率2MHz),静态维持电流为1mA。CMOS/SOI4kb静态随机存储器采用1.2μm单层多晶、双层金属的SOI CMOS抗辐照工艺技术,其六管存储单元尺寸较小:12.8μm×8.4μm,芯片尺寸为:3.6mm×3.84mm。Abstract: A kind of CMOS/SOI 4kb Static RAM’s which adopts 1k×4 asynchronous system was investigated.To reduce power and improve the speed of circuit,the static RAM’s uses Double-Word-Line,Address-Transition-Detecti on and two stage amplifier technologies,so it achieves the fast access time:30ns.1.2μm SOI CMOS technology of single poly and doublelevel metal is developed for CMOS/SOI 4kb SRAM,storage size: 12.8μm×8.4μm,chip size:3.6mm×3.84mm.
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