Abstract: CMP used in copper Damascene process make metal thickness variability through full-chip severely because of pattern dependant within die.For accurate interconnect metric in 90nm process,we propose a novel method which can implement statistical analysis for the impact of metal thickness variation in CMP efficiently,by modeling interconnect with the parasitical parameters’ means and standard deviations extracted from TCAD.Experiment shows the method is very practical interconnect simulation in 90nm process.