新型低压超结功率VDMOS器件数值模拟

Simulation of new low voltage super junction Power VDMOS

  • 摘要: 由于"Silicon Limit"的限制,VDMOS的导通电阻不能很大程度的降低,为了突破这一极限,超结VDMOS结构被采用,本文采用氮化硅硬掩模和高能硼注入在n型外延层中形成交替的p型区从而形成超结结构。利用ISE-TCAD模拟器进行工艺器件模拟,模拟结果表明击穿电压最大有40%的提高,同时导通电阻也有明显的降低。采用高能注入形成超结VDMOS为减小VDMOS导通电阻提供了一种切实有效的方法。

     

    Abstract: VDMOS(Vertically Double Diffused Metal Oxide Semiconductor)Technology for power devices was constrained by the Silicon Limit.It is now improved to have linear relation between On Resistance(Ron) and Breakdown voltage(BV) instead of the quadratic relation by super junction VDMOS.The body junction is modified with the addition of a high energy implantation that forms super junction VDMOS.We use ISE-TCAD simulator to simulate the Ron and BV of the super junction VDMOS.The results show a maximum 40 % increase in BV and obvious reduction in Ron.The approach with a high energy implantation provides a simple means to reduce the on resistance of the VDMOS.

     

/

返回文章
返回