多晶硅栅耗尽导致的SRAM单比特位失效分析

Analysis of SRAM single bit failure due to local poly depletion

  • 摘要: 本文分析了一种静态随机存储器单比特位失效的机理。通过纳米探针测量,发现该比特位写操作失败是由负责存取的N型晶体管的驱动力较弱导致。TEM分析显示该晶体管的多晶硅栅中晶粒尺寸较大,这有可能导致栅的功函数变化以及靠近栅介质层区域的掺杂较轻。我们用SPICE模拟证实了晶体管驱动力变弱的原因是局域的多晶栅耗尽。

     

    Abstract: A SRAM single bit failure at write mode was carefully analyzed.By nano-probing the failed bit,it was found that a weak access-NMOS disabled the write-operation of that particular bit.ATEM check showed that the failed bit has large poly grain size as compared to a normal bit,which causes the gate work function to change and lower the local arsenic concentration.It is then verified by SPICE simulation that the local poly depletion is the origin of the access-NMOS conductibility degradation.

     

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