SiGe沟道CMOS器件可靠性研究进展与挑战

Research progress and challenges in SiGe channel CMOS device reliability

  • 摘要: 综述硅锗(SiGe)沟道互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)器件在可靠性方面的研究进展与挑战。随着CMOS技术向纳米尺度持续发展至5 nm工艺节点,SiGe沟道因能够提升空穴迁移率,已成为高性能p型场效应晶体管(p-type field-effect transistor, pFET)的重要选择之一,并有望在更小尺寸节点中得到广泛应用。首先分析SiGe pFET在负偏置温度不稳定性(negative bias temperature instability, NBTI)方面的显著改善效果,其物理机制涉及能带偏移与应力效应,能够有效降低空穴被界面陷阱捕获的概率;随后探讨SiGe CMOS的正偏置温度不稳定性(positive bias temperature instability, PBTI)、氧化层击穿(breakdown, BD)、热载流子注入(hot carrier injection, HCI)退化、低频噪声(low-frequency noise, LFN)及自热效应(self-heating effect, SHE)等可靠性问题。研究表明,SiGe技术在改善NBTI的同时,也伴随着PBTI退化、关态漏电增加以及自热积累加剧等新的挑战。结合物理机理分析各项可靠性问题的根源,提出通过沟道组分调控、界面工程与器件结构优化,实现先进SiGe CMOS性能与可靠性的协同提升。

     

    Abstract: This review provides an overview of recent advancements and challenges in the reliability of SiGe channel complementary metal oxide semiconductor (CMOS) devices. As CMOS technology scales down to the 5 nm node and beyond, SiGe channels have become a promising solution for high-performance p-type field-effect transistor (pFET) due to their superior hole mobility, with potential extensive application in further scaled nodes. The article begins by analyzing the significant improvement in negative bias temperature instability (NBTI) observed in SiGe pFET, attributing this enhancement to band offset and strain effects that effectively reduce hole trapping at interface states. It then evaluates other critical reliability concerns, such as positive bias temperatureinstability (PBTI), oxide breakdown (BD), hot carrier injection (HCI) degradation, low-frequency noise (LFN), and self-heating effect (SHE) in SiGe-based CMOS devices. Research indicates that while SiGe technology demonstrates notable advantages in mitigating NBTI, it also introduces new challenges, including PBTI degradation, increased off-state leakage current, and exacerbated self-heating. By investigating the physical mechanisms behind these reliability issues, this review suggests that advanced SiGe CMOS technology can achieve the co-optimization of performance and reliability through channel composition engineering, interface optimization, and device structure improvements.

     

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