SiGe 沟道器件高k界面钝化技术研究进展与挑战

Progress and challenges in high-k/SiGe interface passivation technology for SiGe channel devices

  • 摘要: 硅锗(SiGe)合金因其高空穴迁移率、优异的抗负偏压温度不稳定性(NBTI)性能以及灵活的阈值电压可调性,在5 nm及以下节点的p型场效应晶体管(pFETs)中展现出重要的应用前景,成为突破传统硅基CMOS器件物理极限的关键材料。然而,高k/SiGe栅极堆叠界面由于Si与Ge氧化活性差异,容易形成氧化锗(GeOX)与锗富集层(Ge-rich layer, GRL),导致界面态密度(Dit)过高,严重制约了SiGe器件性能的充分发挥。目前,尽管针对界面钝化的研究已取得一定进展,但现有技术仍存在明显局限:Si-cap技术难以适配高Ge含量的SiGe材料,且在3D器件中的应用能力较弱;Ge清除法依赖退火条件;Al/S/N元素钝化对热预算敏感,难以全面满足先进器件的需求。从SiGe器件的发展现状出发,系统阐述了高k/SiGe界面质量调控的必要性,重点综述了主流界面钝化技术的最新研究进展。基于现有瓶颈,提出了多种工艺结合、强化可靠性的未来发展方向,为推进高迁移率 SiGe 技术的规模化国产应用提供了理论指导与技术参考。

     

    Abstract: SiGe, characterized by high hole mobility, excellent NBTI resistance, and flexible threshold - voltage tunability, exhibits significant potential for sub-5 nm p-type field-effect transistors (pFETs). It plays a crucial role in overcoming the physical limitations of conventional silicon-based CMOS devices. However, at the high-k/SiGe interface, the differing oxidation activity between Si and Ge leads to the formation of GeOx and a GRL, resulting in a high interface state density (Dit) that severely limits the performance of SiGe devices. Despite advancements in interface passivation research, current techniques face notable limitations. The Si-capping method demonstrates poor compatibility with high-Ge-content SiGe and 3D devices, while the Ge-removal approach is highly dependent on specific annealing conditions. Additionally, Al/S/N - based passivation is sensitive to thermal budgets, thereby failing to fully satisfy the requirements of advanced devices. Based on the current state of SiGe device development, this paper highlights the necessity for regulating high-k/SiGe interface quality, reviews recent progress in mainstream interface passivation technologies, and proposes future research directions, such as multi-process integration and reliability enhancement. These insights provide valuable guidance and references for the large-scale domestic application of high-mobility SiGe technology.

     

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