Abstract: In advanced packaging, silicon through-silicon vias (TSVs) face significant reliability challenges under mechanical vibration and thermal stress loads. This study constructs three-dimensional finite element models incorporating gradient void and crack defect ratios of 20%, 40%, and 60% to systematically investigate the mechanical response of TSVs under random vibration and thermal cycling conditions. Model validation is performed through thermal cycling experiments. Results demonstrate that under random vibration loading, the equivalent stress at critical locations in void-defect models increases significantly with higher void ratios, whereas crack-defect models exhibit no clear correlation between crack ratio and stress response. Under thermal cycling, both void and crack defects induce elevated stress levels that scale proportionally with defect ratio; furthermore, void expansion progressively intensifies and shows a positive correlation with contact impedance variation. Extraction of RLC parameters reveals that void defect extension substantially increases the equivalent resistance of the TSV structure, thereby degrading its electrical performance. Experimental results confirm that as the number of temperature cycles increases, void defects in TSVs grow larger, exhibiting a positive correlation with changes in contact resistance.