Abstract: Phase change memory represents an advanced non-volatile memory technology that utilizes the resistivity difference between the crystalline and amorphous states of chalcogenide compounds to achieve data storage. It is anticipated to emerge as a next-generation mainstream storage solution due to its high-speed operation, high density, low power consumption, compatibility with CMOS processes, and resistance to electromagnetic interference and radiation. However, its asymmetric read-write characteristics present significant challenges to further advancements. This paper introduces a data granularity conversion scheme for quad serial peripheral interface (QSPI) phase change memory aimed at optimizing read and write performance. To enhance write speed, a "writing mask" design is incorporated into the QSPI phase change memory, enabling a sequential write clock frequency of up to 80 MHz. Additionally, the read efficiency of the phase change memory is improved through the adoption of a pre-reading technique. Simulation results demonstrate that the proposed read/write strategy significantly enhances the communication speed of the QSPI while maintaining the operational reliability of the phase change memory.