Abstract: SiGe, characterized by high hole mobility, excellent negative bias temperature instability (NBTI) resistance, and flexible threshold-voltage tunability, exhibits significant potential for sub-5 nm p-type field-effect transistors (pFETs). It plays a crucial role in overcoming the physical limitations of conventional silicon-based complementary metal oxide semiconductor (CMOS) devices. However, at the high-k dielectric/SiGe interface, the differing oxidation activity between Si and Ge leads to the formation of GeO_x and a Ge-rich layer (GRL), resulting in a high interface state density (D_it) that severely limits the performance of SiGe devices. Despite advancements in interface passivation research, current techniques face notable limitations. The Si-capping method demonstrates poor compatibility with high-Ge-content SiGe and 3D devices, while the Ge-removal approach is highly dependent on specific annealing conditions. Additionally, Al/S/N-based passivation is sensitive to thermal budgets, thereby failing to fully satisfy the requirements of advanced devices. Based on the current state of SiGe device development, this paper highlights the necessity for regulating high-k dielectric/SiGe interface quality, reviews recent progress in mainstream interface passivation technologies, and proposes future research directions, such as multi-process integration and reliability enhancement. These insights provide valuable guidance and references for the large-scale domestic application of high-mobility SiGe technology.