Abstract: Superconducting digital circuits, characterized by extremely low power consumption and picosecond switching speeds, are considered key candidates for high-performance computing systems in the post-Moore's Law era. However, compared with mature superconducting logic technologies, high-performance, scalable cryogenic memory technologies remain relatively underdeveloped, creating a critical bottleneck that restricts the advancement of superconducting digital computing systems. This paper systematically reviews the research progress and architectures of cryogenic memory technologies. First, the core challenges in memory design under cryogenic conditions are analyzed, including compatibility issues with superconducting logic circuits and storage density bottlenecks. Subsequently, from the perspective of the memory hierarchy, superconducting shift registers, caches based on superconducting matrix random-access memory, and main memory schemes based on cryo-CMOS are reviewed. The advantages and disadvantages of these technical approaches are compared in terms of speed, density, power consumption, and scalability. Finally, interface circuit technologies required to achieve efficient interconnection between superconducting caches and semiconductor main memory, including clock matching and signal amplification mechanisms, are discussed, and future development directions for superconducting hierarchical memory systems are outlined.